1. Field of the Invention
The present disclosure generally relates to integrated circuits, and more particularly to raised self-aligned silicide contacts.
2. Background of Invention
The technological development of micro-sized semiconductor integrated circuit devices has required improved methods for making conductive contacts to the semiconductor impurity regions. Metal silicides have proven to be excellent contact materials, which can be readily formed in a self-aligned manner by a salicidation process.
Formation of metal silicide contacts through the salicidation process typically involves the steps of depositing a thin metal layer (e.g., less than about 15 nm in thickness) that contains a silicide metal or metal alloy (i.e., a metal or metal alloy that is capable of reacting with silicon to form metal silicide) uniformly over a semiconductor substrate that contains both silicon-containing device regions and dielectric isolation regions, heating the semiconductor substrate to form silicide over the device regions, and then selectively etching away the un-reacted metal from the dielectric isolation regions.
Silicide formation and morphology control with known methods is not reliable and precise enough for semiconductor devices with a gate length less than 20 nm. Current methods produce non-uniform silicide depth and non-uniform encroachment of the silicide beneath the gate stack. Encroachment of the silicide beneath the gate stack occurs when metal diffuses and reacts too deep vertically or laterally into the substrate and interacts with crystalline defects. This non-uniformity limits production yield and device performance. Yield may be reduced due to junction leakage and device short circuits while device performance is compromised by high parasitic resistance.
Further, current silicidation methods for forming metal silicides on SiGe substrates having high concentrations of Ge have thermal stability and roughness issues. When a silicide forms on a SiGe substrate, the Ge is incorporated into the silicide replacing Si atoms. The high concentration of Ge decreases the melting point of the silicide and therefore enhances the diffusion of atoms at lower temperatures. This increased diffusion of atoms is undesirable and produces unwanted non-uniformity in the resulting silicide. The non-uniformity results in a very rough interface between the silicide and the substrate with variations in vertical thickness as large as two times the intended thickness of the silicide. Further, these thickness variations cause agglomeration during subsequent processing.
In addition to the stability and roughness issues, high concentrations of Ge in a silicide decrease the process window for the selective etch technique. Standard selective etch chemistries used in self-aligned silicide formation such as sulfuric peroxide and aqua regia, become less selective to the germanosilicide, which may lead into yield issues.
There is therefore a continuing need for an improved method for fabricating the silicide contacts on semiconductor substrates, which is capable of both controlling the silicide morphology and producing more robust thermally stable metal silicides on SiGe substrates.